Level shifters are utilized in a variety of applications in which it is desired to couple a circuit node to either of two voltage levels in dependence upon the state of an input control signal. FIG. 1 is a simplified illustration of a driver applied to a high side FET of a buck converter. The converter comprises FETs 10 and 12, inductor 14 and capacitor 16. The junction of FETs 10 and 12 and inductor 14 is indicated as SW. Various other converter and controller elements are not shown as they are not necessary for explanation of the broad operation. Output VOUT of the converter is maintained at a lower voltage level than the input voltage VIN. FETs 10 and 12 are alternatively activated in succession. As VIN is greater than VOUT, activation of FET 10 permits charging of output capacitor 16 through inductor 14 as current builds in the inductor. When FET 12 is activated, current through inductor begins to decrease. The time activation of the FET switches is regulated to maintain the output voltage at the desired level.
Activation and deactivation of FET 10 is under the control of driver 18. When FET 10 is in the conductive state, the voltage at its gate exceeds the voltage at the inductor side source. For non-conduction, the gate voltage should not exceed the source voltage. In response to controlled input signals, driver 18 shifts the level of voltage applied to the gate of FET 10 between VBOOST and VSW to control the states of the FET. Capacitor 17 is coupled between the VBOOST and VSW nodes. In a first state, VBOOST is applied to the gate of FET 10. The gate to source voltage, VBOOST−VSW activates FET 10 to a conductive condition. In a second state, VSW is applied to the gate of FET 10. As there is no potential difference between the gate and the source, FET 10 is not conductive.
A known level shifting circuit is illustrated in FIG. 2. An input signal transmission stage 20 comprises PMOS FETs 22 and 24, NMOS FETs 26 and 28 and inverter 30. FETs 22 and 26 are coupled in series across voltage reference line 32 and ground, as are series FETs 24 and 28. The gate of FET 22 is coupled to the drain of FET 28. The gate of FET 24 is coupled to the drain of FET 26. The gate of FET 26 is coupled to a select signal input. The gate of FET 28 is coupled to the select signal input through inverter 30. The output, line N1, of stage 20 is coupled to the junction of the gate of FET 24 and the drain of FET 26.
An output stage 40 comprises PMOS FET 42 coupled in series with NMOS FET 44 across voltage reference line 32 and reference line 34. The junction 36 of FETs 42 and 44 is coupled to the gate of FET 10. In response to controlled input signals, driver 18 shifts the level of voltage V36 applied to the gate-source of FET 10 between a level of VBOOST−VSW volts and zero volts. Junction 36 will either be coupled to line 32, VBOOST, via FET 42 or to line 34, VSW, via FET 44.
Coupled between signal transmission stage 20 and output stage 40 is logic circuit 50. Inverter 52 is coupled between line N1 and one input of NAND gate 54. Inverter 52 is also coupled to one input of NAND gate 56 via inverter 58. The output of NAND gate 54 is coupled to the other input of NAND gate 56. The output of NAND gate 56 is coupled to the other input of NAND gate 54 via inverters 60 and 62. The output of NAND gate 54 is coupled to the gate of FET 42. Inverter 60 is coupled to the gate of FET 44. Logic circuit 50 is responsive to the state of the signal at N1 to provide a gating signal to one of the output stage FETs and prevents simultaneous conduction of both output stage FETs.
With a high level input signal VSIG at stage 20, FET 26 is biased conductive, FET 28 is biased non-conductive, FET 24 is biased conductive, and FET 22 is biased non-conductive. Line N1 is at a low level state under these conditions. The coupling of N1 by inverters 52 and 58 imposes a low level signal to the input of NAND gate 56. NAND gate 56 outputs a high level signal that is inverted by inverter 60. The low level output is applied to FET 44 to bias it to a non-conductive state. Both inputs of NAND gate 54 are at a high level by virtue of inverters 52 and 62. NAND gate 54 outputs a low signal that biases FET 42 to a conductive state. Output line 36 thus is coupled to line 32.
With a low level input signal at stage 20, FET 26 is biased non-conductive, FET 28 is biased conductive, FET 24 is biased non-conductive, and FET 22 is biased conductive. Line N1 is at a high level state under these conditions. The coupling of N1 by inverter 52 imposes a low level signal to the input of NAND gate 54. NAND gate 54 outputs a high level signal to bias FET 42 to a non-conductive state. Both inputs of NAND gate 56 are high to produce a low level output, which is inverted by inverter 60 to bias FET 44 to a conductive state. Output line 36 is thus coupled to line 34.
The level of the input signal to input stage 20 thus selects whether line 36 is coupled to line 32 or line 34. When line 36 is coupled to line 32, output FET is conductive, and when line 36 is coupled to line 34, FET is non-conductive. When the input transitions between level states, delays occur in the input stage 20, as illustrated in FIG. 3. The voltage input signal, VSIG, is exemplified by a square wave waveform. Corresponding waveforms for the signals at N1 (VN1−VSW) and line 36 (V36−VSW) are represented. At time t1, the input signal changes from a low level state to a high level state. In response, N1 changes state from a high level to a low level with a slight delay incurred by the transition of input stage FET 26 to the conductive state. The state of output line 36 then changes from the lower level to the higher level. The total delay between the rising transition of the input signal and the time t2, at which the output line 36 reaches its high state, is relatively short. At time t3, the input signal reverts to the low level state. Input stage FET 22 is responsive to this change in input signal, via interaction of inverter 30 and FET 28, to conduct to provide a high level at N1. Full conduction occurs with a delay that is significantly greater than the transition of FET 22 to non-conduction. The state of output line 36 then changes from the higher level to the lower level at time t4.
The delay of the output in response in response to an input signal transition from high level to low level is significantly greater than the delay in response to the low to high input signal transition. The conventional level shifter produces faster High-to-Low transitions than Low-to-High transitions because FETs 22 and 24 must be made weaker devices than FETs 26 and 28 for proper operation. The prior art circuit thus does not produce a level shift functionality that satisfactorily equalizes transition delays in both directions. A level shift circuit that provides the same rising and falling delay is needed. Capability of making both delays equal to the shorter delay of the prior art circuit would be particularly desirable.